The present invention relates to the manufacture of very large scale integrated (VLSI) circuits and, more particularly, to the enhancement of photolithographic images through the use of phase shifted masks.
A very large scale integrated (VLSI) complementary metal oxide semiconductor (CMOS) chip is manufactured on a silicon wafer by a sequence of material additions (i.e., low pressure chemical vapor depositions, sputtering operations, etc.), material removals (i.e., wet etches, reactive ion etches, etc.), and material modifications (i.e., oxidations, ion implants, etc.). These physical and chemical operations interact with the entire wafer. For example, if a wafer is placed into an acid bath, the entire surface of the wafer will be etched away. In order to build very small electrically active devices on the wafer, the impact of these operations has to be confined to small, well defined regions.
Lithography in the context of VLSI manufacturing of CMOS devices is the process of patterning openings in photosensitive polymers (sometimes referred to as photoresists or resists) which define small areas in which the silicon base material is modified y a specific operation in a sequence of processing steps. The manufacturing of CMOS chips involves the repeated patterning of photoresist, followed by an etch, implant, deposition, or other operation, and ending with the removal of the expended photoresist to make way for the new resist to be applied for another iteration of this process sequence.
The basic lithography system consists of a light source, a stencil or photo mask containing the pattern to be transferred to the wafer, a collection of lenses, and a means for aligning existing patterns on the wafer with patterns on the mask. The aligning may take place in an aligning step or steps and may be carried out with an aligning apparatus. Since a wafer containing from 50 to 100 chips is patterned in steps of 1 to 4 chips at a time, these lithography tools are commonly referred to as steppers. The resolution, R, of an optical projection system such as a lithography stepper is limited by parameters described in Raleigh""s equation:
R=k xcex/NA, 
where xcex represents the wavelength of the light source used in the projection system and NA represents the numerical aperture of the projection optics used. xe2x80x9ckxe2x80x9d represents a factor describing how well a combined lithography system can utilize the theoretical resolution limit in practice and can range from about 0.8 down to about 0.5 for standard exposure systems. The highest resolution in optical lithography is currently achieved with deep ultra violet (DUV) steppers operating at 248 nm wavelengths of 356 nm are also in widespread use and 193 nm wavelength lithography is becoming commonplace.
Conventional photo masks consist of chromium patterns on a quartz plate, allowing light to pass wherever the chromium has been removed from the mask. Light of a specific wavelength is projected through the mask onto the photoresist coated wafer, exposing the resist wherever hole patterns are placed on the mask. Exposing the resist to light of the appropriate wavelength causes modifications in the molecular structure of the resist polymers which, in common applications, allow a developer to dissolve and remove the resist in the exposed areas. Such resist materials are known as positive resists. (Negative resist systems allow only unexposed resist to be developed away.) The photo masks, when illuminated, can be pictured as an array of individual, infinitely small light sources which can be either turned on (points in clear areas) or turned off (points covered by chrome). If the amplitude of the electric field vector which describes the light radiated by these individual light sources is mapped across a cross section of the mask, a step function will be plotted reflecting the two possible states that each point on the mask can be found (light on, light off).
These conventional photo masks are commonly referred to as chrome on glass (COG) binary masks, due to the binary nature of the image amplitude. The perfectly square step function of the light amplitude exists only in the theoretical limit of the exact mask plane. At any given distance away from the mask, such as in the wafer plane, diffraction effects will cause images to exhibit a finite image slope. At small dimensions, that is, when the size and spacing of the images to be printed are small relative to the xcex/NA, electric field vectors of adjacent images will interact and add constructively. The resulting light intensity curve between the image features is not completely dark, but exhibits significant amounts of light intensity created by the interaction of adjacent features. The resolution of an exposure system is limited by the contrast of the projected image, that is, the intensity difference between adjacent light and dark image features. An increase in the light intensity in nominally dark regions will eventually cause adjacent features to print as one combined structure rather than discrete images.
As VLSI lithography is being challenged to deliver manufacturable patterning solutions at unprecedented resolution levels, strong resolution enhancement techniques (RET) are becoming increasingly popular. Techniques such as sub-resolution-assist-features (SRAF) combined with off-axis-illumination (OAI) and attenuated phase shifted mask (PSM), alternating phase shifted mask (altPSM), or dipole feature decomposition offer the possibility of doubling the resolution of conventional lithography (see Liebmann et al., xe2x80x9cTCAD Development for Lithography Resolution Enhancement,xe2x80x9d IBM J. Res. and Dev., Vol. 45, no. 5 (September 2001), pp. 651-665). This increased resolution is bought at the cost of complex layout manipulations (for example, see Liebmann et al., xe2x80x9cOptimizing Style Options for Sub-Resolution Assist Features,xe2x80x9d in Optical Microlithography XIV (C. Progler, ed.), Proceedings of SPIE, Vol. 4346 (2001), pp. 141-152). Post tape-out or post-layout implementation of strong RET (i.e., implementation of RET after physical design and verification), is limited in scope and effectiveness. To realize the full potential of strong RET, layout optimization has to occur at the physical design level. AltPSM was the first RET to clearly demonstrate the need for deep integration into the design flow (see Liebmann et al., xe2x80x9cEnabling Alternating Phase Shifted Mask Designs for a Full Logic Gate Level: Design Rules and Design Rule Checking,xe2x80x9d in Design Automation Conference 2001 (Jun. 18-22, 2001), pp.79-84) and will be used here to exemplify the concept of integrated RET layout optimization.
The quality with which small images can be replicated in lithography depends largely on the available process window; that is, that amount of allowable dose and focus variation that still results in correct image size. Phase shifted mask (PSM) lithography improves the lithographic process window or allows operation at a lower k value by introducing a third parameter on the mask. The electric field vector, like any vector quantity, has a magnitude and direction, so, in addition to turning the electric field amplitude on and off, it can be turned on with a phase of about 0xc2x0 or turned on with a phase of about 180xc2x0. This phase variation is achieved in PSMs by modifying the length that a light beam travels through the mask material. By recessing the mask to an appropriate depth, light traversing the thinner portion of the mask and light traversing the thicker portion of the masks will be 180xc2x0 out of phase, that is, their electric field vector will be of equal magnitude but point in exactly the opposite direction so that any interaction between these light beams result in perfect cancellation. However, because the 180xc2x0 phase transition forces a minimum in the image intensity, narrow dark lines will be printed. These unwanted residual phase images are erased using a trim mask, which is a second mask that transmits light only in regions left unexposed by the residual phase edge.
Alternating Phase Shifted Mask (altPSM) lithography is a resolution enhancement technique (RET) that is rapidly gaining acceptance as a viable solution to meet aggressive integrated circuit (IC) technology scaling time-lines. Delays in next generation optical and non-optical lithography tooling add vital importance to successful implementation of altPSM. AltPSM takes advantage of destructive interference of light to double the achievable resolution of an optical lithography system. Stated another way, this resolution enhancement technique results in a k-factor that has a theoretical limit of 0.25, rather than 0.5 as in conventional lithographic techniques. The light interference is created by selectively manipulating the topography of the photomask to introduce an appropriate path-length difference in the imaging light. The design of the altPSM involves disposing phase shifting shapes on opposing sides of the sub-cutoff dimension, where one phase shape is assigned a phase shift that is 180xc2x0 out of phase from that of the opposing phase shape.
In addition to being assigned opposite phases, these phase shapes or regions need to obey a variety of lithographic, mask manufacturability, and design rules governing their size and spacings. Thus, layout decisions must be made regarding the size, spacing, and phase assignment of these phase shapes relative to the layout of circuit elements. Some rules are mutually opposing and require careful optimization. This manipulation of the mask topography requires phase information to be added to the circuit layout in the computer-aided design (CAD) system (see, for example, Russell et al., xe2x80x9cSystem and Method for Verifying a Hierarchical Circuit Desing,xe2x80x9d U.S. Pat. No. 5,528,508). Key to the successful implementation of altPSM is an efficient electronic design automation (EDA) tool that can convert circuit designs to altPSM layouts with minimal impact to layout design density or design complexity. A phase shifting program creates phase shapes of appropriate width, spacing, and color (i.e. phase assignment) for an altPSM compliant layout and reports conflicts for a non-compliant layout (see, for example, Liebmann et al., xe2x80x9cPhase Shifted Mask Design System, Phase Shifted Mask and VLSI Circuit Devices Manufactured Therewith,xe2x80x9d U.S. Pat. No. 6,057,063, hereinafter referred to as Liebmann et al. xe2x80x2063). The conflicts reported only describe regions where the phase assignment fails. It is not trivial to provide useful insight on how and where to resolve the conflicts, due to the complex topological interlock of phase shapes.
Methods to assign and optimize phases in an altPSM design are known in the art, for example, as described in U.S. Pat. Nos. 5,537,648 and 5,636,131 (hereinafter, Liebmann et al. xe2x80x2648) and Liebmann et al. xe2x80x2063. FIG. 1 illustrates a flow chart typical of such methods. After creating an initial circuit layout (Block 401), the design of the altPSM (Block 400) is performed. Critical circuit elements having critical dimension CD are identified, as indicated in Block 410 of FIG. 1. Phase shapes are defined in association with each critical element (Block 420). Then the phase shapes are legalized according to the various rules as discussed below (Block 430). Next, the appropriate phases are assigned to each phase shape (Block 440), ensuring binary coloring across the entire mask layout. A method for performing binary coloring is described, for example, in Kim et al., xe2x80x9cAutomatic Generation of Phase Shift Masks Using Net Coloring,xe2x80x9d U.S. Pat. No. 5,883,813 (hereinafter referred to as Kim et al. xe2x80x2813). The phase coloring method of Kim et al. xe2x80x2813 involves the formation of nets of phase shapes by creating a xe2x80x9cconnectedxe2x80x9d function that links or couples phase shapes across critical elements as intrusion pairs, meaning that the phase of one shape determines the phase of the other shape in the intrusion pair. The xe2x80x9cconnectedxe2x80x9d function also includes shapes that are close enough the be phase coupled. xe2x80x9cClose enoughxe2x80x9d could mean that there must be a minimum phase-to-phase spacing, which will be discussed further below. After the phase have been assigned in conformance with the various rules, the layout is checked for any inconsistencies or errors (Block 450). If layout conforms with all rules, then the altPSM design is accepted and the associated trim mask is then designed (Block 409). Since it may not be possible to correct all such errors, it may be necessary to accept a loss in process window, or re-design the circuit layout (Block 460).
An altPSM legalization program (e.g. Block 430) attempts to make a VLSI layout altPSM compliant so that phase shapes can be created successfully. There are two basic approaches.
In the first approach, design rules between design shapes are derived from the constraints among phase shapes and constraints between phase shapes and design shapes. It then turns to a traditional design rule correction approach to legalize the layout based on the derived rules (see, for example, Heng et al., xe2x80x9cApplication of Automated Design Migration to Alternating Phase Shift Mask Design,xe2x80x9d Proceedings, 2001 International Symposium on Physical Design, (Apr. 1-4, 2001), pp. 38-43). This approach has worked well in practice but has two significant limitations:
1. Some complex topological configurations that cause phase shift non-compliance over long distances and involving many individual phase transitions, commonly referred to as odd-even runs, cannot be captured and enforced by local, shapes-centric design rules. An odd-even run is illustrated in FIG. 2 showing vertically oriented critical design elements 710, 711, 712, 713, 714, 715 and 716. Phase shift shapes 120, 130, 140, 150, 160, 170 and 180 are disposed on opposing sides of each of the design elements, but the requirement of 180xc2x0 phase shift on opposing sides of each critical element cannot be achieved for this layout configuration.
2. As resolution limits continue to tighten lithography process windows, it is becoming increasingly necessary to locally optimize phase shift design parameters. That is, where in the past, phase width was a constant for a given technology generation, now phase width depends on local layout details (see, for example, commonly assigned co-pending application Ser. No. 10/014,707). Enhanced altPSM (see, for example, Wong et al., xe2x80x9cAlternating Phase-Shifting Mask with Reduced Aberration Sensitivity: Lithography Considerations,xe2x80x9d in Optical Microlithography XIV (C. Progler, ed.), Proceedings of SPIE, Vol 4346 (2001), pp. 420-428), improves aberration insensitivity by adding secondary phase regions to more isolated phase edges. Overall, this added complexity in the phase parameters makes it so difficult as to be virtually impossible or impractical to convert phase design parameters to layout design rules.
In the second approach, a graph theoretical technique (see Kahng et al., xe2x80x9cNew Graph Bipartizations for Double-Exposure, Bright Field Alternating Phase-Shift Mask Layout,xe2x80x9d Design Automation Conference, Asia and South Pacific, Proceedings of ASP-DAC 2001 (January, 2001), pp.133-138; and Kahng et al. xe2x80x9cOptimal Phase Conflict Removal for Layout of Alternating Phase-Shifting Masks,xe2x80x9d PCT Application, WO 01/20502, 22 March 2001) is used to describe the topological conflict between phase shapes of rectangular design shapes. However, the graph theoretical method of Kahng et al. has two major drawbacks:
1. The conflict graph is constructed based on predefined rectangular phase shapes and identifies phase conflicts based on overlapping of these predefined rectangular phase shapes.
2. It provides for conflict resolution by only two types of layout modifications, namely, increasing the spacing between two critical features or by increasing the width of a critical feature.
Thus, the method of Kahng et al. does not model the legality of phase shapes explicitly, and will not allow conflict resolution by changing or merging phase shapes, or other solutions such as modifying both phase shapes and critical features. The graph theoretical analysis of Kahng et al. fails to provide a solution for T-junctions.
In view of the foregoing discussion, there is a need to provide for a method for optimizing an altPSM design layout that flexibly integrates rules and constraints for both critical design features and phase shift features, and allows conflict resolution of complex layout configurations, as well as optimization of phase shapes.
In accordance with the present invention, an integrated approach is described for producing a conflict-free, resolution-enhanced alternating phase shift layout by combining RET layout manipulation with a layout legalization process.
The RET layout manipulation process of the present invention includes creation of a phase interlock graph that is created to capture the topological interaction (i.e., phase interlock) between phase shapes, without pre-determining the size and shape of phase shifting shapes. The phase interlock graph of the present invention does not pre-determine the merging or splitting of interacting phase shapes based on their existing proximity, but instead represents potential interaction or interlocking between phase shapes and lets, the conflict analysis process determine whether interacting phase shapes should be merged or should be split.
In accordance with the present invention, the phase interlock graph is constructed from nodes identifying design elements and their topological relationship without predetermining the shapes and dimensions of those design elements. Nodes representing critical design segments (i.e., those design elements having critical dimensions to be printed) may be identified by using an interior Voronoi diagram, also known as medial axis (see Lee, D. T., xe2x80x9cMedial Axis Transformation of a Planar Shape,xe2x80x9d IEEE Transactions on Pattern Analysis and Machine Intelligence, Vol. PAMI-4, no. 4 (July 1982), pp. 363-369) of a general polygon. Nodes that represent the interactions between phase shapes may be determined by bisectors between phase shape representors which act as placeholders for phase shapes in the altPSM design. One method for determining the bisector between phase shape representors is to construct an exterior Voronoi diagram that is exterior to the polygons that form the critical design elements of the initial layout (see Papadopoulou, E., xe2x80x9cLoo Voronoi Diagrams and Applications to VLSI Layout and Manufacturing,xe2x80x9d in Proceedings, Ninth International Symposium on Algorithms and Computation (Dec. 14-16, 1998), pp. 9-18). If two edges of two phase shapes share a common Voronoi bisector, they have the potential to interfere with each other. A built-in or pre-determined distance may be used to prune unnecessary interaction, so that, for example, phase shapes that are too far will not interact. The phase interlock graph captures the interaction between interfering phase shapes, the planarity of the voronoi diagram guarantees the planarity of the phase interlock graph.
Since the phase interlock graph is a planar graph by construction, the planarity property of the interlock graph is used to analyze the nature of the phase conflict violations. This topological pattern analysis can be used to categorized and recognize a set of topological conflict patterns for which conflict resolution solutions may be associated, empirically or otherwise. This topological pattern analysis pinpoints the location within the layout where the conflict occurs and where corrections to the layout should be made to resolve the conflict.
The cost of resolving each type of conflict may be taken into consideration, for example, by using layout slack. Conflicts may be resolved by any of a variety of methods, including, for example, widening of a region of a critical shape segment or the entire critical shape segment, or merging or splitting of adjacent phase shapes. The conflict resolution solution selected results in a set of layout constraints that will ensure the legality of the layout at the location of the identified conflict.
The layout may then be legalized in accordance with the layout constraints, preferably using a minimum perturbation criterion (see, for example, Heng et al., xe2x80x9cA VLSI Artwork Legalization Technique Based on a New Criterion of Minimum Layout Perturbation,xe2x80x9d in Proceedings, 1997 International Symposium on Physical Design (Apr. 14-16, 1997), pp. 116-121) or other cost analysis criteria. Since more than one method of resolving a local conflict may be applicable, a set of legalized layouts may be produced. Note that not all local conflict resolution solutions will necessarily result in a legal layout. Among the set of legalized layouts, the most economical one is preferably chosen, based on factors such as area (i.e. slack), deviation from the original layout, and the manufacturability of the layout, among other possible factors.